參數(shù)資料
型號(hào)： M68HC16Y1CFC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP16
封裝： QFP-160
文件頁(yè)數(shù)： 92/138頁(yè)
文件大?。?/td> 784K
代理商： M68HC16Y1CFC
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
57
3.8.2 Port E
Port E can be made available in all operating modes. The state of BERR and DATA8 during reset con-
trols whether the port E pins are used as bus control signals or discrete I/O lines.
If the MCU is in emulator mode, an access of the port E data, data direction, or pin assignment registers
(PORTE, DDRE, PEPAR) is forced to go external. This allows port replacement logic to be supplied ex-
ternally, giving an emulator access to the bus control signals.
PORTE is a single register that can be accessed in two locations. It can be read or written at any time
the MCU is not in emulator mode.
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input. This register can be read or written at any
time the MCU is not in emulator mode.
The bits in this register control the function of each port E pin. Any bit set to one defines the correspond-
ing pin to be a bus control signal, with the function shown in the following table. Any bit cleared to zero
defines the corresponding pin to be an I/O pin, controlled by PORTE and DDRE.
* When PEPA3 is set, the PE3 pin goes to logic level one. The CPU16 does not support the control function for this
pin.
PORTE — Port E Data Register
$YFFA11, $YFFA13
76543210
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
UUUUUUUU
DDRE — Port E Data Direction Register
$YFFA15
76543210
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
DDE1
DDE0
RESET:
00000000
PEPAR — Port E Pin Assignment Register
$YFFA17
76543210
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
RESET (Expanded, Single-chip):
DATA8
00000000
Table 19 Port E Pin Assignments
PEPAR Bit
Port E Signal
Bus Control Signal
PEPA7
PE7
SIZ1
PEPA6
PE6
SIZ0
PEPA5
PE5
AS
PEPA4
PE4
DS
PEPA3
PE3
—*
PEPA2
PE2
AVEC
PEPA1
PE1
DSACK1
PEPA0
PE0
DSACK0
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