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參數(shù)資料
| 型號： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 35/138頁 |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
13
Relative modes are used for branch and long branch instructions. A byte or word signed twos comple-
ment offset is added to the program counter if the branch condition is satisfied. The new PC value, con-
catenated with the PK field, is the effective address.
Post-modified index mode is used with the MOVB and MOVW instructions. A signed 8-bit offset is add-
ed to index register X after the effective address formed by XK and IX is used.
In M68HC11 systems, direct mode can be used to perform rapid accesses to RAM or I/O mapped into
page 0 ($0000 to $00FF), but the CPU16 uses the first 512 bytes of page 0 for exception vectors. To
compensate for the loss of direct mode, the ZK field and index register Z have been assigned reset ini-
tialization vectors — by resetting the ZK field to a chosen page, and using 8-bit unsigned index mode
with IZ, a programmer can access useful data structures anywhere in the address map.
2.7 Instruction Set
The CPU16 has an 8-bit instruction set. It uses a prebyte to support a multipage opcode map. This ar-
rangement makes it possible to fetch an 8-bit operand simultaneously with a page 0 opcode. If a pro-
gram makes maximum use of 8-bit offset indexed addressing mode, it will have a significantly smaller
instruction space.
The instruction set is based upon that of the M68HC11, but the opcode map has been rearranged to
maximize performance with a 16-bit data bus. All M68HC11 instructions are supported by the CPU16,
although they may be executed differently. Most M68HC11 code will run on the CPU16 following reas-
sembly. The user must take into account changed instruction times, the interrupt mask, and the new
interrupt stack frame.
The CPU16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned
multiplication and division. New instructions have been added to support extended addressing and dig-
ital signal processing.
The following table is a summary of the CPU16 instruction set. Because it is only affected by a few in-
structions, the LSB of the condition code register is not shown in the table — instructions which affect
the interrupt mask and PK field are noted.
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