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| 型號： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 86/138頁 |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
51
NOTES:
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
3. The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
3.6 Reset
Reset procedures handle system initialization and recovery from catastrophic failure. The
MC68HC16Y1 performs resets with a combination of hardware and software. The SCIM determines
whether a reset is valid, asserts control signals, performs basic system configuration and boot ROM se-
lection based on hardware mode-select inputs, then passes control to the CPU16.
Reset occurs when an active low logic level on the RESET pin is clocked into the SCIM. Resets are
gated by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous
reset can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If
there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are
clocked to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
SCIM Reset Mode Selection
The logic states of certain MCU pins during reset determine SCIM operating configuration. Refer to 3.2
Operating Modes for more information.
3.6.1 MCU Module Pin Function During Reset
As a general rule, module pins default to port functions, and input/output ports are set to input state.
This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the
appropriate port data direction registers. Refer to individual module sections in this technical summary
for more information. The following table is a summary of module pin functions out of reset.
Table 16 Operand Transfer Cases
Transfer Case
SIZ1
SIZ0
ADDR0
DSACK1
DSACK0
DATA
[15:8]
DATA
[7:0]
Byte to 8-bit Port (Even/Odd)
0
1
X
1
0
OP0
(OP0)
Byte to 16-bit Port (Even)
0
1
0
X
OP0
(OP0)
Byte to 16-bit Port (Odd)
0
1
0
X
(OP0)
OP0
Word to 8-bit Port (Aligned)
1
0
1
0
OP0
(OP1)
Word to 8-bit Port (Misaligned)
1
0
1
0
OP0
(OP0)
Word to 16-bit Port (Aligned)
1
0
X
OP0
OP1
Word to 16-bit Port (Misaligned)
1
0
1
0
X
(OP0)
OP0
3 Byte to 8-bit Port (Aligned)2
1
0
1
0
OP0
(OP1)
3 Byte to 8-bit Port (Misaligned)2
1
0
OP0
(OP0)
3 Byte to 16-bit Port (Aligned)3
1
0
X
OP0
OP1
3 Byte to 16-bit Port (Misaligned)2
1
0
X
(OP0)
OP0
Long Word to 8-bit Port (Aligned)
0
1
0
OP0
(OP1)
Long Word to 8-bit Port (Misaligned)3
1
0
1
0
OP0
(OP0)
Long Word to 16-bit Port (Aligned)
0
X
OP0
OP1
Long Word to 16-bit Port (Misaligned)3
1
0
1
0
X
(OP0)
OP0
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