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參數(shù)資料
| 型號： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 6/138頁 |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
103
MIVR — MCCI Interrupt Vector Register
MIVR determines which vector the CPU uses to service an MCCI interrupt after it is acknowledged. At
reset, MIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the exception
vector table. MIVR must be programmed to one of the user-defined vectors ($40–$FF) during initializa-
tion of the MCCI in order for interrupts to be serviced.
MCCI interrupt vectors are adjacent to one another in the exception vector table. MIVR[7:2] are the
same for all three interfaces. The MCCI provides the values for MIVR[1:0] according to the source of
the interrupt (%00 for SCIA, %01 for SCIB, and %10 for the SPI). Writes to MIVR[1:0] have no meaning
or effect. Reads of MIVR[1:0] return a value of %11.
ILSPI determines the priority of interrupts requested by the SPI. The ILSPI field must contain a value
between $1 (lowest priority) and $7 (highest priority) for interrupts to be recognized. If ILSPI, ILSCIA,
and ILSCIB are the same, simultaneous interrupt requests are recognized in SPI, SCIA, SCIB priority.
7.1.2 MCCI Pin Control Registers
MCCI pin control registers determine the use of eight MCU pins. Although these pins are used by the
serial subsystems, any pin may alternately be assigned to use in a general-purpose parallel port. The
MCCI pin assignment register (PMCPAR) determines whether pins are assigned to the SPI or to the
parallel port. Clearing a bit assigns the corresponding pin to the port; setting a bit assigns the pin to the
SPI. PMCPAR does not affect operation of the SCI submodule.
The MCCI data direction register (DDRMC) determines whether pins are inputs or outputs. Clearing a
bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRMC affects both
SPI function and I/O function. DDRMC determines the direction of SCI TXD pins only when an SCI
transmitter is disabled. When an SCI transmitter is enabled, the TXD pin is an output.
MCCI port data register PORTMC latches I/O data; MCCI pin state register PORTMCP allows pin state
to be read regardless of data direction configuration.
Writes to PORTMC are stored in an internal data latch. If any bit of PORTMC is configured as discrete
output, the latched value is driven onto the corresponding pin. Reads of PORTMC return the value of
the pin only if the pin is configured as a discrete input. Otherwise, the value read is the latched value.
To avoid driving undefined data, first write a byte to PORTMC, then configure DDRMC.
Reads of PORTMCP always return the state of the pins regardless of whether the pins are configured
as input or output. Writes to PORTMCP have no effect.
ILSPI — SPI Interrupt Level Register
$YFFC06
15
14
13
12
11
10
9
8
7
0
ILSPI
0
RESERVED
RESET:
0
PORTMC — MCCI Port Data Register
$YFFC0C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
PMC7
PMC6
PMC5
PMC4
PMC3
PMC2
PMC1
PMC0
PORTMCP — MCCI Port Pin State Register
$YFFC0E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
PMC7
PMC6
PMC5
PMC4
PMC3
PMC2
PMC1
PMC0
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