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| 型號(hào)： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 91/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MOTOROLA
MC68HC16Y1
56
MC68HC16Y1TS/D
Access to port A, B, E, G, and H data and data direction registers and port E pin assignment register
requires three clock cycles, to ensure timing compatibility with external port replacement logic. Port reg-
isters are byte-addressable and are grouped to allow coherent word access to port data register pairs
A-B and G-H, as well as word-aligned long word coherency of A-B-G-H port data registers. Port regis-
ters are not affected by CPU reset.
If emulator mode is enabled, accesses to ports A, B, E, G, and H data and data direction registers and
port E pin assignment register are ignored, and can be replaced with external logic, such as a Motorola
Port Replacement Unit. Port F registers remain accessible.
A write to port A, B, E, F, G, or H data register is stored in the internal data latch, and if any port pin is
configured as an output, the value stored for that bit is driven on the pin. A read of the port data register
returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is
the value stored in the register.
3.8.1 Ports A and B
Ports A and B are available in single-chip mode only. One data direction register controls data direction
for both ports. Port A and B registers can be read or written at any time the MCU is not in emulator mode.
DDA and DDB control the direction of the pin drivers for ports A and B, respectively, when the pins are
configured for I/O. Setting DDA or DDB configures all pins in the corresponding port as outputs. Clear-
ing DDA or DDB to zero configures all pins in the corresponding port as inputs.
Table 18 General-Purpose I/O Ports
Port
Shared Function
Modes
A
ADDR[18:11]
Single chip
B
ADDR[10:3]
Single chip
E
Bus control
All
F
IRQ[7:1]/MODCLK
All
G
DATA[15:8]
Single chip
H
DATA[7:0]
Single chip, 8-bit expanded
PORTA — Port A Data Register
$YFFA0A
76543210
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
UUUUUUUU
PORTB — Port B Data Register
$YFFA0B
76543210
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
UUUUUUUU
DDRAB — Port A/B Data Direction Register
$YFFA14
76543210
000000
DDA
DDB
RESET:
00000000
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