參數(shù)資料
型號： M68HC16Y1CFC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP16
封裝： QFP-160
文件頁數(shù)： 98/138頁
文件大小： 784K
代理商： M68HC16Y1CFC
MOTOROLA
MC68HC16Y1
62
MC68HC16Y1TS/D
3.10 Emulation Mode Chip Select Signals
Emulation mode chip select signals are used during external register or ROM emulation. Pin function is
controlled by a chip select pin assignment register, but the other chip select registers do not affect these
signals.
During emulator mode operation, all port A, B, E, G, and H data and data direction registers, and the
port E pin assignment register are mapped externally. The emulator chip select signal CSE is asserted
when any of these registers is addressed. The SCIM does not respond to these accesses — an external
device, such as a port replacement unit, can respond instead. See 3.3 Emulation Support for more
information.
An internal module chip select signal CSM can also be enabled during emulator mode operation. When
the ROM module is enabled, CSM is asserted when an access to an address assigned to the masked
ROM array is made — this allows an external device to emulate the ROM. Internal DSACK is generated
by the ROM module after it has inserted the number of wait states specied by the WAIT eld in the
MRMCR. See 9 Masked ROM Module for more information.
3.10.1 Chip Select Registers
Pin assignment registers (CSPAR) determine functions of chip select pins. Pin assignment registers
also determine port size (8- or 16-bit) for dynamic bus allocation.
A pin data register (PORTC) latches discrete output data.
Blocks of addresses are assigned to each chip select function. Block sizes of 2 Kbytes to 1 Mbyte can
be selected by writing values to the appropriate base address register (CSBAR). However, because the
logic state of ADDR20 is always the same as the state of ADDR19 in the MC68HC16Y1, the largest
usable block size is 512 Kbytes. Address blocks for separate chip select functions can overlap.
Chip select option registers (CSOR) determine timing of and conditions for assertion of chip select sig-
nals. Eight parameters, including operating mode, access size, synchronization, and wait state insertion
can be specified.
Initialization code often resides in a peripheral memory device controlled by the chip select circuits. A
set of special chip select functions and registers (CSORBT, CSBARBT) is provided to support bootstrap
operation.
Table 22 Chip Select Pin Allocation
Chip Select
Function
Alternate
Function
Discrete Outputs
Function
CSBOOT
—
CS0
BR
—
CSM
BG
—
CSE
BGACK
—
CS3
FC0
PC0
—
FC1
PC1
CS5
FC2
PC2
CS6
ADDR19
PC3
CS7
ADDR20
PC4
CS8
ADDR21
PC5
CS9
ADDR22
PC6
CS10
ADDR23
ECLK
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