
MOTOROLA
MC68341 USER’S MANUAL
7- 17
In either case, the data bits are loaded into the data portion of the stack while the A/D bit
is loaded into the status portion of the stack normally used for a parity error (SR bit 5).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the
place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this
mode may still contain error detection and correction information. One way to provide
error detection, if 7-bit characters are not required, is to use software to calculate parity
and append it to the 5-, 6-, or 7-bit character.
7.3.5 Bus Operation
This section describes the operation of the IMB during read, write, and interrupt
acknowledge cycles to the serial module. All serial module registers must be accessed as
bytes.
7.3.5.1 READ CYCLES. The serial module is accessed by the CPU32 with no wait states.
The serial module responds to byte reads. Reserved registers return logic zero during
reads.
7.3.5.2 WRITE CYCLES. The serial module is accessed by the CPU32 with no wait
states. The serial module responds to byte writes. Write cycles to read-only registers and
reserved registers complete in a normal manner without exception processing; however,
the data is ignored.
7.3.5.3 INTERRUPT ACKNOWLEDGE CYCLES. The serial module is capable of
arbitrating for interrupt servicing and supplying the interrupt vector when it has
successfully won arbitration. The vector number must be provided if interrupt servicing is
necessary; thus, the interrupt vector register (IVR) must be initialized. If the IVR is not
initialized, a spurious interrupt exception will be taken if interrupts are generated.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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