
MOTOROLA
MC68341 USER’S MANUAL
4- 29
periodic timer. This register can be read or written at any time. Bits 15–10 are not
implemented and always return zero when read. A write does not affect these bits.
PITR
$024
15
14
13
12
11
10
9876543210
000000
SWP
PTP
PITR7
PITR6
PITR5
PITR4
PITR3
PITR2
PITR1
PITR0
RESET:
000000
MODCK MODCK
00
00000
Supervisor Only
Bits 15–10—Reserved
SWP—Software Watchdog Prescale
This bit controls the software watchdog clock source as shown in 4.3.2.5 System
Protection Control Register (SYPCR).
1 = Software watchdog clock prescaled by a value of 512.
0 = Software watchdog clock not prescaled.
The SWP reset value is the inverse of the MODCK bit state on the rising edge of reset.
PTP—Periodic Timer Prescaler Control
This bit contains the prescaler control for the periodic timer.
1 = Periodic timer clock prescaled by a value of 512.
0 = Periodic timer clock not prescaled.
The PTP reset value is the inverse of the MODCK bit state on the rising edge of reset.
PITR7–PITR0—Periodic Interrupt Timer Register Bits 7–0
The remaining bits of the PITR contain the count value for the periodic timer. A zero
value turns off the periodic timer.
4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which
the software watchdog servicing sequence is written. The software watchdog can be
enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time, but
returns all zeros when read.
SWSR
$027
76543210
SWSR7 SWSR6 SWSR5 SWSR4 SWSR3 SWSR2 SWSR1 SWSR0
RESET:
00000000
Supervisor Only
4.3.3 Clock Synthesizer Control Register (SYNCR)
The SYNCR can be read or written only in supervisor mode. The reset state of SYNCR
produces an operating frequency of 8.39 MHz when the PLL is referenced to a 32.768-
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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