MOTOROLA
MC68341 USER’S MANUAL
4- 19
If an external device requires additional time to prepare for entry into LPSTOP mode,
entry can be delayed by asserting HALT
(see 3.4.2 LPSTOP Broadcast Cycle ).
4.2.7 Freeze
FREEZE is asserted by the CPU32 if a breakpoint is encountered with background mode
enabled. Refer to Section 5 CPU32 for more information on the background mode. When
FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor continue
to operate normally. However, the software watchdog, the periodic interrupt timer and the
internal bus monitor will be affected. When FREEZE is asserted, setting the FRZ1 bit in
the MCR disables the software watchdog and periodic interrupt timer, and setting the
FRZ0 bit in the MCR disables the bus monitor.
4.3 PROGRAMMING MODEL
Figure 4-8 is a programming model (register map) of all registers in the SIM41. For more
information about a particular register, refer to the description of the module or function
indicated in the right column. The ADDR (address) column indicates the offset of the
register from the address stored in the module base address register. The FC (function
code) column indicates whether a register is restricted to supervisor access (S) or
programmable to exist in either supervisor or user space (S/U).
For the registers discussed in the following pages, the number in the upper right-hand
corner indicates the offset of the register from the address stored in the module base
address register. The numbers on the top line of the register represent the bit position in
the register. The second line contains the mnemonic for the bit. The numbers below the
register represent the bit values after a hardware reset. The access privilege is indicated
in the lower right-hand corner.
NOTE:
A CPU32 RESET instruction will not affect any of the SIM41
registers.
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Freescale Semiconductor, Inc.
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