7- 30
MC68341 USER’S MANUAL
MOTOROLA
RxRDYA—Channel A Receiver Ready or FIFO Full
The function of this bit is programmed by MR1A bit 6.
1 = If programmed as receiver ready, a character has been received in channel A
and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a
character has been transferred from the receiver shift register to the FIFO, and
the transfer has caused the channel A FIFO to become full (all three positions
are occupied).
0 = If programmed as receiver ready, the CPU32 has read the receiver buffer. After
this read, if more characters are still in the FIFO, the bit is set again after the
FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the receiver
buffer. If a character is waiting in the receiver shift register because the FIFO is
full, the bit will be set again when the waiting character is loaded into the FIFO.
TxRDYA—Channel A Transmitter Ready
This bit is the duplication of the TxRDY bit in SRA.
1 = The transmitter holding register is empty and ready to be loaded with a character.
This bit is set when the character is transferred to the transmitter shift register.
This bit is also set when the transmitter is first enabled. Characters loaded into
the transmitter holding register while the transmitter is disabled are not
transmitted.
0 = The transmitter holding register was loaded by the CPU32, or the transmitter is
disabled.
7.4.1.9 INTERRUPT VECTOR REGISTER (IVR). The IVR contains the 7-bit vector
number of the interrupt. When the serial module is enabled (i.e., the STP bit in the MCR is
cleared), this register can be read or written to at any time while in supervisor mode.
IVR
$705
76543210
IVR7
IVR6
IVR5
IVR4
IVR3
IVR2
IVR1
IVR0
RESET:
00001111
Read /Write
Supervisor Only
IVR7–IVR0—Interrupt Vector Bits
Each module that generates interrupts has an interrupt vector field. This 7-bit number
indicates the offset from the base of the vector table where the address of the exception
handler for the specified interrupt is located. The IVR is reset to $0F, which indicates an
uninitialized interrupt condition. See Section 5 CPU32 for more information.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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