10/31/95
SECTION 1: OVERVIEW
UM Rev.1.0
xvi
MC68341 USER’S MANUAL
MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
Section 9
Queued Serial Peripheral Module
9.1
Block Diagram ..................................................................................... 9-1
9.2
Memory Map ....................................................................................... 9-2
9.3
QSPM Pins ......................................................................................... 9-3
9.4
Registers ............................................................................................. 9-4
9.4.1
Overall QSPM Configuration Summary........................................... 9-7
9.4.2
QSPM Global Registers .................................................................. 9-8
9.4.2.1
QSPM Configuration Register (QMCR) ....................................... 9-8
9.4.2.2
QSPM Test Register (QTEST)..................................................... 9-10
9.4.2.3
QSPM Interrupt Level Register (QILR) ........................................ 9-10
9.4.2.4
QSPM Interrupt Vector Register (QIVR) ...................................... 9-11
9.4.3
QSPM Pin Control Registers ........................................................... 9-11
9.4.3.1
QSPM Port Data Register (QPDR) .............................................. 9-12
9.4.3.2
QSPM Pin Assignment Register (QPAR) .................................... 9-12
9.4.3.3
QSPM Data Direction Register (QDDR) ...................................... 9-13
9.5
QSPI Submodule ................................................................................ 9-13
9.5.1
Features .......................................................................................... 9-14
9.5.1.1
Programmable Queue ................................................................. 9-14
9.5.1.2
Programmable Peripheral Chip Selects....................................... 9-14
9.5.1.3
Wraparound Transfer Mode......................................................... 9-14
9.5.1.4
Programmable Transfer Length ................................................... 9-15
9.5.1.5
Programmable Transfer Delay ..................................................... 9-15
9.5.1.6
Programmable Queue Pointer ..................................................... 9-15
9.5.1.7
Continuous Transfer Mode .......................................................... 9-15
9.5.2
Block Diagram ................................................................................. 9-16
9.5.3
QSPI Pins ........................................................................................ 9-16
9.5.4
Programmer's Model and Registers ................................................ 9-17
9.5.4.1
QSPI Control Register 0 (SPCR0) ............................................... 9-18
9.5.4.2
QSPI Control Register 1 (SPCR1) ............................................... 9-20
9.5.4.3
QSPI Control Register 2 (SPCR2) ............................................... 9-22
9.5.4.4
QSPI Control Register 3 (SPCR3) ............................................... 9-24
9.5.4.5
QSPI Status Register (SPSR) ..................................................... 9-25
9.5.4.6
QSPI RAM ................................................................................... 9-26
9.5.4.6.1
Receive Data RAM (REC.RAM) ............................................... 9-27
9.5.4.6.2
Transmit Data RAM (TRAN.RAM)............................................ 9-27
9.5.4.6.3
Command RAM (COMD.RAM) ................................................ 9-27
9.5.5
Operating Modes and Flowcharts ................................................... 9-30
9.5.5.1
Master Mode ................................................................................ 9-37
9.5.5.1.1
Master Mode Operation ........................................................... 9-37
9.5.5.1.2
Master Wraparound Mode........................................................ 9-38
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Freescale Semiconductor, Inc.
For More Information On This Product,
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