MOTOROLA
Page iii
MC68HC05C0 Specification Rev. 1.2
TABLE OF CONTENTS
SECTION 1
INTRODUCTION........................................................... 1
1.1
GENERAL .................................................................................. 1
1.2
FEATURES ................................................................................ 1
1.3
MASK OPTIONS........................................................................ 2
1.4
SIGNAL DESCRIPTION ............................................................ 3
1.4.1
VDD AND VSS ..................................................................... 3
1.4.2
IRQ ....................................................................................... 3
1.4.3
OSC1, OSC2 ........................................................................ 3
1.4.4
RESET.................................................................................. 3
1.4.5
A15,A14-A8 .......................................................................... 3
1.4.6
AD7:0.................................................................................... 3
1.4.7
AS (ADDRESS STROBE)/ CS2 ........................................... 3
1.4.8
RD......................................................................................... 4
1.4.9
WR........................................................................................ 4
1.4.10
A7-A0/PD7-PD0.................................................................... 4
1.4.11
PB4-PB0/SCK,TDO,RDI,TCAP,TCMP ................................. 4
1.4.12
CS1/PB5 ............................................................................... 4
1.4.13
PC3-PC0............................................................................... 4
1.4.14
LIR/MODE ............................................................................ 5
1.5
DEVICE PINOUT ....................................................................... 5
SECTION 2
MEMORY ......................................................................... 9
2.1
EXTERNAL MAPPING EXCEPTIONS .................................... 11
2.2
RAM ......................................................................................... 11
SECTION 3
CPU CORE .................................................................... 13
3.1
REGISTERS ............................................................................ 13
3.1.1
ACCUMULATOR (A) .......................................................... 14
3.1.2
INDEX REGISTER (X)........................................................ 14
3.1.3
PROGRAM COUNTER (PC) .............................................. 14
3.1.4
STACK POINTER (SP)....................................................... 14
3.1.5
CONDITION CODE REGISTER (CCR).............................. 14
3.2
ADDRESSING MODES ........................................................... 15
3.2.1
IMMEDIATE........................................................................ 15
3.2.2
DIRECT .............................................................................. 15
3.2.3
EXTENDED ........................................................................ 15
3.2.4
RELATIVE .......................................................................... 15
3.2.5
INDEXED, NO OFFSET ..................................................... 16
3.2.6
INDEXED, 8-BIT OFFSET.................................................. 16
3.2.7
INDEXED, 16-BIT OFFSET................................................ 16
3.2.8
BIT SET/CLEAR ................................................................. 16
3.2.9
BIT TEST AND BRANCH ................................................... 16
3.2.10
INHERENT ......................................................................... 17