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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 26/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0B |
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Section 5: Resets
MOTOROLA
Page 23
MC68HC05C0 Specification Rev. 1.2
SECTION 5
RESETS
The MCU can be reset five ways. There are four internal reset conditions: the initial power-
on reset (POR) function, a COP watchdog-timer reset, a low-voltage reset (LVR), and an
illegal STOP reset, and one external reset condition: an active low input to the RESET pin.
The four internal conditions cause the RESET pin to be driven low for a minimum of eight
processor clock cycles (tcyc) to allow external peripherals to reset. Any reset will cause the
operating mode and the Muxed/Non-Muxed mode to be relatched on the rising edge or
RESET.
5.1
POWER-ON RESET (POR)
An internal reset is generated on power-up to allow the internal clock generator to stabilize.
The power-on reset is strictly for power turn-on conditions and should not be used to detect
a drop in the power supply voltage. There is a 4064 internal processor clock cycle (tcyc)
oscillator stabilization delay after the oscillator becomes active. If the RESET pin is held low
at the end of this 4064 cycle delay, the MCU will remain in the reset condition until RESET
is driven high.
.
Figure 5-1: Power-On Reset and RESET
RESET
NOTES:
1. Internal timing signal and internal bus information not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
OSC1
2
Internal
Clock
1
Internal
Address
Bus
1
V
DD
Internal
Data
Bus
1
t
RL
New
PCH
New
PCL
Op
Code
Op
Code
PCH
PCL
3
t
cyc
4064t
cyc
t
VDDR
Dummy
FFFF
New
PC
New
PC
FFFE
New
PC
New
PC
FFFE
FFFF
FFFE
Dummy
4064t
cyc
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