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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 83/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0B |
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Section 12: Serial Communications Interface
MOTOROLA
Page 75
MC68HC05C0 Specification Rev. 1.2
After loading the last byte in the serial communications data register and receiving the
TDRE flag, the user can clear TE. Transmission of the last byte will then be completed
before the transmitter gives up control of the TDO and SCK (if enabled) pins. While the
transmitter is active, the data direction register control for Port B bit 3 is overridden and the
line is forced to be the TDO pin. Port B bit 4 is also overridden and forced to be the SCK
pin if SCKM is set in SCCR1.
1= Transmitter enabled
0= Transmitter disabled
RE- Receiver Enable
When the receiver enable bit is set, the receiver is enabled. When RE is clear, the receiver
is disabled and all of the status bits associated with the receiver (RDRF, IDLE, OR, NF and
FE) are inhibited. While the receiver is enabled, the data direction register control for Port
B bit 2 is overridden and the line is forced to be the RDI pin.
1= Receiver enabled
0= Receiver disabled
RWU - Receiver Wake-Up
When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and
enables the wake-up function. If the WAKE bit in SCCR1 is cleared, RWU is automatically
cleared by the SCI logic after receiving 10 (M = 0) or 11 (M = 1) consecutive ones. If the
WAKE bit in SCCR1 is set, RWU is automatically cleared by the SCI logic after receiving a
data word whose MSB is set. See Table 12-1.
1= Receiver wake-up enabled
0= Receiver wake-up disabled
SBK - Send Break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11
(M = 1) zeros and then reverts to idle. If SBK remains set, the transmitter will continually
send whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break
code, the transmitter sends at least logic one to guarantee recognition of a valid start bit. If
the transmitter is currently empty and idle, setting and clearing SBK is likely to queue two
character times of break because the first break transfers almost immediately to the shift
register and the second is then queued into the parallel transmit buffer.
If during a data byte transmission, the TE and SBK bits are toggled, or if SBK is toggled
followed by TE being toggled, a break character will not be sent. Only a preamble will be
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