參數(shù)資料
型號(hào)： MC68HC05C0B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁數(shù)： 57/96頁
文件大小： 357K
代理商： MC68HC05C0B
Section 10: Multi-Function Timer
MOTOROLA
Page 51
MC68HC05C0 Specification Rev. 1.2
Table 10-2: Minimum COP Reset Times
10.5
TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If interrupts are
enabled, a timer interrupt will cause the processor to exit the WAIT mode.
10.6
TIMER DURING STOP MODE
The timer is cleared when going into STOP mode. In addition, the interrupt flags (TOF and
RTIF) and the interrupt enable bits (TOFE and RTIE) in the TCSR are cleared by internal
hardware to remove any pending timer interrupt requests and to disable any further timer
interrupts.When STOP is exited by an external interrupt or an external RESET, the internal
oscillator will resume, followed by an internal processor oscillator stabilization delay (stop
recovery time). The timer is then cleared and operation resumes.
RT1:RT0
16.0 MHz
8.0 MHz
00
57.344 ms
114.688 ms
01
114.688 ms
229.376 ms
10
229.376 ms
458.752 ms
11
28.672 ms
57.344 ms
MINIMUM COP RESET AT
fosc FREQUENCY SPECIFIED:
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