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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 79/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0B |
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Section 12: Serial Communications Interface
MOTOROLA
Page 71
MC68HC05C0 Specification Rev. 1.2
Table 12-1: Method of Receiver Wake-Up
CPOL - Clock Polarity
This bit allows the user to select the polarity of the clock to the SCK pin. This bit works in
conjunction with the CPHA bit to produce the desired clock-data relation.
1= Steady state high outside the transmission window
0= Steady state low outside the transmission window
NOTE:
The CPOL bit should not be changed when the transmitter is enabled.
CPHA - Clock Phase
This bit allows the user to select the phase of the clock to be sent to the SCK pin. This bit
works in conjunction with the CPOL bit to produce the desired clock-data relation.
1= SCK line activated at the beginning of the data bit
0 = SCK line activated in the middle of the data bit
NOTE:
The CPHA bit should not be changed when the transmitter is enabled.
LBCL - Last Bit Clock
This bit allows the user to select whether or not the clock associated with the last data bit
transmitted (MSB) is output to the SCK pin.
1= Clock is active on last data bit
0= Clock is inactive on last data bit
The last data bit is the eighth or ninth bit, depending on the state of the M bit. Refer to Table
12-2 to determine the number of clock pulses transmitted.
WAKE
M
Description
0
X
Detection of an idle line allows the next data byte received
to cause the receive data register to fill and produce an
RDRF flag.
1
0
Detection of a received one in the eighth data bit allows an
RDRF flag and associated error flags.
1
Detection of a received one in the ninth data bit allows an
RDRF flag and associated error flags.
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相關(guān)代理商/技術(shù)參數(shù) |
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