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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 55/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0B |
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MOTOROLA
Section 10: Multi-Function Timer
Page 50
MC68HC05C0 Specification Rev. 1.2
10.3
TIMER COUNTER REGISTER (TCR)
The Timer Counter Register is a read-only register which contains the current value of the
8-bit ripple up-counter at the beginning of the timer chain. This counter is clocked at E
divided by 4 and can be used for various functions including a software input capture.
Extended time periods can be attained using the TOF function to increment a temporary
RAM storage location thereby simulating a 16-bit (or more) counter.
Figure 10-3: Timer Counter Register
The power-on cycle clears the entire counter chain and begins clocking the counter. After
4064 E-cycles, the power-on reset circuit is released which again clears the counter chain
and allows the device to come out of reset. At this point, if RESET is not asserted, the timer
will start counting up from zero and normal device operation will begin. When RESET is
asserted anytime during operation (other than POR), the counter chain will be cleared.
10.4
COMPUTER OPERATING PROPERLY (COP) WATCHDOG RESET
The COP watchdog timer function is implemented on this device by using the output of the
RTI circuit and further dividing it by eight.
The COP is enabled out of reset. The COP can be disabled by writing a logic 0 to the
COPEN bit in the Configuration Register.
If the COP circuit times out, an internal reset is generated and the normal reset vector is
fetched. RESET is also driven low to reset external peripherals. Preventing a COP time-out
is done by writing a logic 0 to bit 0 of address $FFFF at the minimum reset rate. When the
COP is cleared, only the final divide by eight stage (output of the RTI) is cleared.
The minimum COP reset rates are listed in Table 10-2 below. Because it is not readily
possible to determine the state of the divider chain ahead of the COP circuit, the COP
should be reset within a period equivalent to seven real-time interrupts, rather than the
eight that one might expect.
76543210
RD
WR
0
RST
$09
0
TCR
0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
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