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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 62/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0B |
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MOTOROLA
Section 11: 16-Bit Timer
Page 56
MC68HC05C0 Specification Rev. 1.2
comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing the MSB ($0E), the
output compare function is inhibited until the LSB ($0F) is also written. The user must write
both bytes (locations) if the MSB is written first. A write made only to the LSB ($0F) will not
inhibit the compare function. The free-running counter is updated every four internal bus
clock cycles. The minimum time required to update the output compare register is a
function of the program rather than the internal hardware.
The processor can write to either byte of the output compare register without affecting the
other byte. The output level (OLVL) bit is clocked to the output level register even if the
output compare flag (OCF) is still set from a previous compare.
Figure 11-6: Timer Output Compare MSB Register
Figure 11-7: Timer Output Compare LSB Register
11.4
INPUT CAPTURE REGISTER
Two 8-bit registers which make up the 16-bit input capture register are read-only and are
used to latch the value of the free-running counter after the corresponding input capture
edge detector senses a defined transition. The level transition which triggers the counter
transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the
contents of the input capture register.
The result obtained by an input capture will be one more than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This
delay is required for internal synchronization. Resolution is one count of the free-running
counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each
proper signal transition regardless of whether the input capture flag (ICF) is set or clear.
The input capture register always contains the free-running counter value that corresponds
to the most recent input capture.
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
RD
WR
U
RST
76543210
OCR
MSB
$0E
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
RD
WR
U
RST
76543210
OCR
LSB
$0F
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05C0CP | 制造商:Motorola Inc 功能描述: |
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| MC68HC05C12P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
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