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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 43/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0B |
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Section 9: Address/Data Bus Interface
MOTOROLA
Page 39
MC68HC05C0 Specification Rev. 1.2
SECTION 9
ADDRESS/DATA BUS INTERFACE
Bus timing is determined by the chosen expanded bus mode, and whether clock stretching
is active. The internal bus frequency is a divide-by-four of the oscillator frequency OSC1.
9.1
MODE SELECTION
The 68HC05C0 has two possible expanded bus modes: Muxed Mode and Non-Muxed
Mode. In Muxed Mode, the data is multiplexed with the lower order 8 address bits. In Non-
Muxed Mode, address and data have individual, separate output. The mode is determined
by the logic value on the LIR/MODE pin at the rising edge of RESET as shown below.
Table 9-1: Bus Modes
Once the mode is established at the rising edge of reset, this pin can be used as LIR. See
Section 8 SYSTEM CONFIGURATION. If LIR is not desired, the MODE pin may be
hardwired. LIR always follows the same timing as the upper address byte A15:A8.
9.2
MUXED MODE BUS TIMING
Figure 9-1: Muxed Mode Timing
MODE PIN
BUS MODE
0
Non-Muxed
1
Muxed
tash
trwhas
taddsu
taddh
tash
trdsu
trdh
ttf
twdsu
twdh
tvarwl
trl
twl
address
data in
data out
address
OSC1
AS
AD7:0
A15:8,CS1~
RD~
WR~
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