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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 37/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0B |
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Section 8: System Configuration
MOTOROLA
Page 33
MC68HC05C0 Specification Rev. 1.2
SECTION 8
SYSTEM CONFIGURATION
This section describes all the system options. Described are expanded bus modes, chip
selects, a Configuration Register, and the External Interrupt Control/Status Register. The
Configuration Register includes internal read visibility, load instruction register visibility,
clock stretching, COP and Low-Voltage Reset enables, chip-select type and enable, STOP
recovery time and enable. The External Interrupt Control/Status Register contains request,
enable, acknowledge, and edge-level sensitivity options for both the external interrupt and
the KEY interrupt.
8.1
EXPANDED BUS MODES
There are two expanded bus modes available on the MC68HC05C0. The bus mode is
specified by the value on the LIR/MODE pin. See Section 9.1 MODE SELECTION for more
information on selecting the bus mode.
8.1.1
MUXED MODE
In Muxed Mode, the lower order address lines (A7-A0) are muxed with the data lines (D7-
D0) on pins 17 - 24 (40 Pin DIP). An address strobe (AS) is available on pin 7 (40 Pin DIP)
for external latching of the address. In this configuration, Port D comprises pins 25 - 32 (40
Pin DIP).
8.1.2
NON -MUXED MODE
In Non-Muxed mode, the lower order address lines (A7-A0) are available on pins 25 - 32
(40 Pin DIP) and the lower order data lines (D7-D0) are available on pins 17 - 24 (40 Pin
DIP). Pin 7 (40 Pin DIP) is available as an additional chip select (CS2).
8.2
CHIP SELECTS
In Non-Muxed Mode, both CS1 and CS2 are active chip selects. In Muxed Mode, only CS1
is available (CS2 is shared with AS). In muxed mode the type for CS1 can be configured
by the user, as specified in the Configuration Register bits CS1P1:0. In Non-Muxed mode
CS1 and CS2 default to a Page-0 chip select type and General Purpose chip select type,
respectively. PB5 defaults to a general purpose port pin out of reset. Therefore CS1 must
be enabled in either mode. The A15 chip select is always present.
8.2.1
PAGE-0 CHIP SELECT TYPE
Addresses in page 0 which are mapped external are selected by this chip select type. See
Section 2 MEMORY. When the Page-0 chip select type is chosen by CS1P1:0, clock
stretching can also be enabled or disabled. Clock stretching will stretch accesses in the
address range $0030 through $003F. See Section 9 ADDRESS/DATA BUS INTERFACE
for more information on clock stretching.
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