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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 18/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0B |
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MOTOROLA
Section 3: CPU Core
Page 16
MC68HC05C0 Specification Rev. 1.2
next instruction. The span of relative addressing is from -128 to +127 from the address of
the next opcode. The programmer need not calculate the offset when using the Motorola
assembler, since it calculates the proper offset and checks to see that it is within the span
of the branch.
3.2.5
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective address of the argument is
contained in the 8-bit index register. This addressing mode can access the first 256
memory locations. These instructions are only one byte long. This mode is often used to
move a pointer through a table or to hold the address of a frequently referenced I/O or RAM
location.
3.2.6
INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the unsigned byte following the opcode
byte. The addressing mode is useful for selecting the K
th element in an n element table.
With this two-byte instruction, K would typically be in X with the address of the beginning of
the table in the second byte of the instruction. As such, tables may begin anywhere within
the first 256 addressable locations and could extend as far as location 510 ($1FE). This is
the last location which can be accessed in this way.
3.2.7
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the two unsigned bytes following the
opcode byte. This addressing mode can be used in a manner similar to indexed, 8-bit offset
except that this three-byte instruction allows tables to be anywhere in memory. As with
direct and extended addressing, the Motorola assembler determines the shortest form of
indexed addressing.
3.2.8
BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and
the byte following the opcode specifies the direct addressing of the byte in which the
specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory,
including I/O, can be selectively set or cleared with a single two-byte instruction.
3.2.9
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit that is to be tested and its condition (set or clear) is included in the
opcode. The address of the byte to be tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third byte is added to the PC if the
specified bit is set or cleared in the specified memory location. This single three-byte
instruction allows the program to branch based on the condition of any readable bit in the
first 256 locations of memory. The span of branching is from -128 to +127 from the address
of the next opcode. The state of the tested bit is also transferred to the carry bit of the
condition code register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05C0P | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC05C0FN | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC05C12AFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| MC68HSC05C12AB | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42 |
| MC68HSC05C12ACP | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05C0CP | 制造商:Motorola Inc 功能描述: |
| MC68HC05C12 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12CP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
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