參數(shù)資料
型號(hào)： MC68HC05C0B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁數(shù)： 65/96頁
文件大?。?/td> 357K
代理商： MC68HC05C0B
Section 11: 16-Bit Timer
MOTOROLA
Page 59
MC68HC05C0 Specification Rev. 1.2
11.6
TIMER STATUS REGISTER (TSR)
The TSR is a read-only register containing three status flag bits.
.
Figure 11-11: Timer Status Register
ICF - Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture edge detector
0 = Flag cleared when TSR and input capture low register ($0D) are accessed
OCF - Output Compare Flag
1 = Flag set when output compare register contents match the free-running counter
contents
0 = Flag cleared when TSR and output compare low register ($0F) are accessed
TOF - Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to $0000 occurs
0 = Flag cleared when TSR and counter low register ($11) are accessed
Bits 0-4 - Not used
Always read zero
Accessing the timer status register satisfies the first condition required to clear status bits.
The remaining step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running
counter at random times to measure an elapsed time. Without incorporating the proper
precautions into software, the timer overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set, and
2. The LSB of the free-running counter is read but not for the purpose of
servicing the flag.
The counter alternate register at address $12 and $13 contains the same value as the free-
running counter (at address $10 and $11); therefore, this alternate register can be read at
any time without affecting the timer overflow flag in the timer status register.
11.7
TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If interrupts are
enabled, a timer interrupt will cause the processor to exit the WAIT mode.
76543210
RD
WR
0
RST
$0B
0
TSR
0
ICF
OCF
TOF
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