參數(shù)資料
型號: MC68HC05C0B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42
封裝: SDIP-42
文件頁數(shù): 76/96頁
文件大小: 357K
代理商: MC68HC05C0B
Section 12: Serial Communications Interface
MOTOROLA
Page 69
MC68HC05C0 Specification Rev. 1.2
12.6
REGISTERS
There are five different registers used in the SCI: SCDAT, SCCR1, SCCR2, SCSR and
BAUD. The internal configuration of these registers is discussed in the following
paragraphs.
12.6.1
SERIAL COMMUNICATIONS DATA REGISTER (SCDAT)
Figure 12-7: Serial Communications Data Register
The Serial Communications Data Register (SCDAT) performs two functions in the serial
communications interface. It acts as the read-only receive data register when it is read and
as the write-only transmit data register when it is written. Figure 12-2shows this register
as two separate registers, namely: the receiver data register (RDR) and the transmit data
register (TDR).
The TDR provides the parallel interface from the internal data bus to the transmit shift
register. The RDR provides the interface from the receive shift register to the internal data
bus.
12.6.2
SERIAL COMMUNICATIONS CONTROL REGISTER 1 (SCCR1)
The SCI Control Register 1 (SCCR1) contains control bits to determine word length, select
wake-up method, and control the options to output the transmitter clock for synchronous
transmissions.
Figure 12-8: Serial Communications Control Register
R8 - Receive Data Bit 8
This bit is the ninth serial data bit received when the SCI system is configured for nine data
bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred
into this bit at the same time as the remaining eight bits (bits 0 – 7) are transferred from the
serial receive shifter to the SCI receive data register. A write to this bit has no effect. In
addition, If M=0 a read from this bit is undefined.
RD
WR
RST
76543210
SCDR
$18
U
DA0
DA1
DA2
DA7
DA6
DA5
DA4
DA2
U
UUU
U
RD
WR
RST
76543210
SCCR1
$15
0
LBCL
CPHA
CPOL
T8
SCKM
M
WAKE
0
000
0
R8
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