參數(shù)資料
型號： MC68HC05C0B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁數(shù)： 63/96頁
文件大小： 357K
代理商： MC68HC05C0B
Section 11: 16-Bit Timer
MOTOROLA
Page 57
MC68HC05C0 Specification Rev. 1.2
After a read of the input capture register ($0C) MSB, the counter transfer is inhibited until
the LSB ($0D) is also read. This characteristic causes the time used in the input capture
software routine and its interaction with the main program to determine the minimum pulse
period.
A read of the input capture register LSB ($0D) does not inhibit the free-running counter
transfer since they occur on opposite edges of the internal bus clock.
Figure 11-8: Timer Input Capture MSB Register
Figure 11-9: Timer Input Capture LSB Register
11.5
TIMER CONTROL REGISTER (TCR)
The TCR is a read/write register containing seven control bits. Three bits control interrupts
associated with the timer status register flags ICF, OCF and TOF.
Figure 11-10: Timer Control Register
ICIE - Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCIE - Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
U
76543210
ICR
MSB
$0C
RD
WR
RST
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
RD
WR
U
RST
76543210
ICR
LSB
$0D
OLVL
IEDG
0
ICM
OCM
TOIE
OCIE
ICIE
RD
WR
0
RST
76543210
TCR
$0A
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