Universal Serial Bus (USB)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
12-19
7
CRC_ERR
CRC error generation enable. This bit enables CRC error generation for debug and test purpose.
In order to use this feature, the DEBUG bit must be set. Enabling this bit causes a CRC error on
the next data packet transmitted. The CRC_ERR bit must be set again in order to generate
another CRC error. This bit only applies to IN transfers. This command bit is write-only and always
returns 0 when read.
1 CRC error generation if DEBUG = 1
0 default value
6
—
Reserved, should be cleared.
5–4
OUT_LVL
Endpoint 0 OUT FIFO level for interrupt. This field selects the FIFO level to generate an OUT_LVL
interrupt. The OUT_LVL interrupt is generated when the FIFO fills above the selected level.
00 FIFO 25% Full
01 FIFO 50% Full
10 FIFO 75% Full
11 FIFO 100% Full
3–2
IN_LVL
Endpoint 0 IN FIFO level for interrupt. This field selects the FIFO level to generate an IN_LVL
interrupt. The IN_LVL interrupt is generated when the FIFO falls below the selected level.
00 FIFO 25% Empty
01 FIFO 50% Empty
10 FIFO 75% Empty
11 FIFO 100% Empty
1
IN_DONE
This bit controls the USB's response to IN tokens from the host. This bit is set at Reset and must
be cleared by software when the last byte of a transfer has been written to the IN-FIFO. This bit is
then subsequently set by the USB core when an end of transfer (EOT) event occurs indicating that
the transfer has been completed. An end of transfer (EOT) event is indicated by one of the
following:
a) An IN packet is transmitted that contains less than the maximum number of bytes defined at
endpoint configuration.
b) A zero length IN packet is transmitted. This occurs when the previously transmitted IN packet
was full, and no more data remains in the IN-FIFO. Hence a single zero length packet must be
sent to indicate EOT.
0 CPU has completed writing to the IN-FIFO and transfer is in progress. The USB module will
send any amount of data in the FIFO or a zero-length packet when the FIFO is empty.
1 Transfer completed or CPU Busy writing transfer into the IN-FIFO. The USB module will only
send maximum size packets or NAK responses if the FIFO contains less than a maximum size
packet. This bit is set at Reset and on an EOT event.
0
—
Reserved, should be cleared.
Table 12-12. EP0CTL Field Descriptions (continued)
Bits
Name
Description