Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-7
Because the presentation of HDLC encoded data on the physical interface is lsb first, the lsb is
right-aligned in the transmit and receive shift register.
A D-channel byte is formed by concatenating two D bits from each of four frames. This data is also
right-aligned in the D-channel receive register as shown in
Figure 13-7.Figure 13-7. D-Channel HDLC Encoded and Unencoded Data.
13.2.3.4
D-Channel Unencoded Data
As with the B channel, a mechanism is provided to support incoming D channels containing unencoded
data, even though as of this document’s publication date, no communication protocols using unencoded
D-channel data are known.
As with unencoded (PCM encoded) B-channel data, it is assumed unencoded D-channel information is
presented on the physical line msb first. The msb is left-aligned in the transmit and receive shift register,
that is, the first bit received is aligned in the msb position through to the last received bit of a byte that is
aligned in the lsb position.
A D-channel byte is formed by concatenating two D bits from each frame over four consecutive frames as
shown in
Figure 13-7. These 8 bits are also left-aligned in the D-channel receive register, that is, the first
two D-channel bits from the first frame go into the two msbs, B7 and B6, the next two D-channel bits from
the second frame in B5 and B4, and so on, until the last two D-channel bits in the fourth frame are aligned
in B1 and B0.
DCL
FSR
Din/Dout
D0 D1
Frame 0
Frame 1
Frame
32
1
0
D7
D6
D5
D4
D3
D2
D1
D0
D2 D3
D4 D5
D6 D7
Frame 2
Frame 3
Din/Dout
D7 D6
D5 D4
D3 D2
D1 D0
Unencoded
HDLC
Encoded
8-Bit D-Channel Receive/Transmit Register, RD, TD