Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-15
13.5
PLIC Registers
Any bits in the following registers marked 0 have no function. When the register is a read/write register,
these bits should be cleared.
Some registers are described that control more than one port. In these cases, parentheses indicates to which
port the control bits relate; for example, LM0(0) is the LM0 bit for port 0.
13.5.1
B1 Data Receive Registers (P0B1RR–P3B1RR)
All bits in these registers are read only and are set on hardware or software reset.
The PnB1RRs contain the last four frames of data received on channel B1. (P0B1RR is the B1 channel
data for port 0, P1B1RR is B1 for port 1, and so on.) The data are packed from the least significant byte
(LSB), up to the most significant byte (MSB).
These registers are aligned on longword boundaries from MBAR + 0x300 for P0B1RR to
frame and bit alignment within the 32-bit word.
31
24
23
16
Field
Frame 0
Frame 1
Reset
1111_1111
R/W
Read Only
15
8
7
0
Field
Frame 2
Frame 3
Reset
1111_1111
R/W
Read Only
Addr
MBAR + 0x300 (P0B1RR); 0x304 (P1B1RR); 0x308 (P2B1RR); 0x30C (P3B1RR)
Figure 13-13. B1 Receive Data Registers P0B1RR–P3B1RR