Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-41
Figure 13-40. Standard IDL2 10-Bit Mode
In the above example, CODEC 1 transmits and receives in the B3 time slot once the U transceiver has
completed the D channel. From the rising edge of FSC1, this is at least 19 DCL clocks later. In
Figure 13-40, a short, optional delay, is shown between the end of the D channel and the start of the B3
channel. For example, let us say this is 1 DCL clocks long. This defines the programmable delay 1 value
to be 20, (19 + 1), or 0x0014. The DFSC3 signal synchronizes CODECs 3 and 4, and the rising edge of
this frame sync occurs 20 clocks after DFSC2, therefore 40 DCL clocks after FSC1. This defines the value
for programmable delay 3 to be 40, (19 + 1 + 20), or 0x0028.
13.6.5
Example 3: Two-Line Remote Access with Ports 0 and 1
In this example, ports 0 and 1 are connected to two S/T transceivers. Ports 0 and 1 are programmed in
slave mode. Ports 2 and 3 are not used, and may be disabled.
Figure 13-41. Two-Line Remote Access
B1
B2
D
U Transceiver
B3
B4
B5
B6
CODEC 1
CODEC 2
CODEC 3
CODEC 4
DCL
FSC1
DFSC2
DFSC3
Din1/
Dout1
D
MC145574 #1
Interface 1
Tx
Rx
IDL SYNC
IDL CLK
Din0
Dout0
FSC0
DCL0
Interface 0
DGrant
DRequest
DGNT0
DREQ0
Din1
Dout1
FSC1
DCL1
DGNT1
DREQ1
Tx
Rx
IDL SYNC
IDL CLK
DGrant
DRequest
MC145574 #2
MCF5272