Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-13
13.3.2
Super Frame Sync Generation
Figure 13-11 shows the generation of the 2-KHz super frame sync. The choice of either FSC0 or FSC1 is
possible using P1CR[FSM]. This allows either the port 0 or port 1 timing to be used to generate the 2-KHz
super frame sync interrupt. The SFSC block then divides this accordingly. When P1CR[FSM] is set, FSC1
is the source of the super frame sync. In case P1CR[MS] is 0 (that is, port 1 is in slave mode), the interrupt
is ultimately driven by an external source. In case the M/S bit is 1 (that is, port 1 is in master mode), FSC1
ultimately comes from port 0.
13.3.3
Frame Sync Synthesis
Figure 13-11 illustrates the relationships between the various frame sync clocks. DFSC1 is generated
through programmable delay 1 referenced to DFSC0. DFSC2 and DFSC3 are generated through
programmable delays 2 and 3 referenced to DFSC1. Note well the following:
P0SDR settings affect DFSC[0–3]
P1SDR settings affect DFSC[1–3]
P2SDR settings affect only DFSC2
P3SDR settings affect only DFSC3
13.4
PLIC Register Memory Map
Table 13-1 lists the PLIC registers with their offset address from MBAR and their default value on reset.
Table 13-1. PLIC Module Memory Map
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x0300
Port0 B1 Data Receive (P0B1RR)
0x0304
Port1 B1 Data Receive (P1B1RR)
0x0308
Port2 B1 Data Receive (P2B1RR)
0x030C
Port3 B1 Data Receive (P3B1RR)
0x0310
Port0 B2 Data Receive (P0B2RR)
0x0314
Port1 B2 Data Receive (P1B2RR)
0x0318
Port2 B2 Data Receive (P2B2RR)
0x031C
Port3 B2 Data Receive (P3B2RR)
0x0320
Port0 D Data Receive
(P0DRR)
Port1 D Data Receive
(P1DRR)
Port2 D Data Receive
(P2DRR)
Port3 D Data Receive
(P3DRR)
0x0328
Port0 B1 Data Transmit (P0B1TR)
0x032C
Port1 B1 Data Transmit (P1B1TR)
0x0330
Port2 B1 Data Transmit (P2B1TR)
0x0334
Port3 B1 Data Transmit (P3B1TR)
0x0338
Port0 B2 Data Transmit (P0B2TR)
0x033C
Port1 B2 Data Transmit (P1B2TR)