IEEE 1149.1 Test Access Port (JTAG)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
21-4
Freescale Semiconductor
21.4
Boundary Scan Register
The boundary scan register contains bits for all device signal and clock pins and associated control signals.
Bidirectional pins include a single scan bit for data (IO.Cell) as shown in
Figure 21-6. These bits are
controlled by an enable cell, shown in
Figure 21-5. The control bit value determines whether the
bidirectional pin is an input or an output. One or more bidirectional data bits can be serially connected to
a control bit as shown in
Figure 21-7. Note that when bidirectional data bits are sampled, bit data can be
interpreted only after examining the I/O control bit to determine pin direction.
Open-drain bidirectional bits require separate input and output cells as no direction control is available
from which to determine signal direction. Programmable open-drain signals also have an enable cell
(XXX.de) to select whether the pin is open drain or push-pull. Signals with pull-up or pull-down resistors
have an associated enable cell (XXX.pu); one enable cell can control multiple resistors.
Figure 21-3. Output Cell (O.Cell) (BC–1)
MUX
Update DR
G1
1 = EXTEST, CLAMP, HI-Z
0 = Otherwise
To output
buffer
To next
cell
Shift DR
From last
cell
Clock DR
Data from
system
logic
1
MUX
G1
1
1 D
C1
1 D
C1