參數(shù)資料
型號(hào)： MCV18ET-I/SO
元件分類： 微控制器/微處理器
英文描述： FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO18
封裝： 7.50 MM, LEAD FREE, SOIC-18
文件頁(yè)數(shù)： 18/108頁(yè)
文件大?。?/td> 1509K
代理商： MCV18ET-I/SO
2009 Microchip Technology Inc.
DS41399A-page 17
MCV18E
2.2.2.5
PIR1 Register
This register contains the individual flag bits for the
peripheral interrupts.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User
software
should
ensure
the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0
R/W-0
U-0
R/W-0
—ADIF
—
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIF: A/D Interrupt Flag bit
1
= A/D conversion complete
0
= A/D conversion has not completed or has not been started
bit 5-3
Unimplemented: Read as ‘0’
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare Mode
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1
= Timer2 to PR2 match occurred (must be cleared in software)
0
= Timer2 to PR2 match has not occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1
= Timer1 register overflowed (must be cleared in software)
0
= Timer1 has not overflowed
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