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MCV18E
DS41399A-page 72
2009 Microchip Technology Inc.
9.8
Time-out Sequence
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
and
depict
time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
synchronize more than one MCV18E device operating
in parallel.
Table 9-5 shows the Reset conditions for some Special
Function Registers, while
Table 9-6 shows the Reset
conditions for all the registers.
9.9
Power Control/STATUS Register
(PCON)
The Power Control/STATUS Register, PCON has two
bits.
Bit 0 is the Brown-out Reset Status bit, BOR. If the
BOREN Configuration bit is set, BOR is ‘1’ on Power-
on Reset and reset to ‘0’ when a Brown-out condition
occurs. BOR must then be set by the user and checked
on subsequent resets to see if it is clear, indicating that
another Brown-out has occurred.
If the BOREN Configuration bit is clear, BOR is
unknown on Power-on Reset.
Bit 1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 9-4:
STATUS BITS AND THEIR SIGNIFICANCE
Oscillator Configuration
Power-up or Brown-out
Wake-up from Sleep
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 TOSC
1024 TOSC
RC
72 ms
—
POR
BOR
TO
PD
0x
1
Power-on Reset (BOREN = 0)
01
1
Power-on Reset (BOREN = 1)
0x
0
x
Illegal, TO is set on POR
0x
x
0
Illegal, PD is set on POR
10
1
Brown-out Reset
11
0
1
WDT Reset
11
0
WDT Wake-up
11
u
MCLR Reset during normal operation
11
1
0
MCLR Reset during Sleep or interrupt wake-up from Sleep