參數(shù)資料
型號(hào)： MCV18ET-I/SO
元件分類： 微控制器/微處理器
英文描述： FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO18
封裝： 7.50 MM, LEAD FREE, SOIC-18
文件頁(yè)數(shù)： 84/108頁(yè)
文件大小： 1509K
代理商： MCV18ET-I/SO
2009 Microchip Technology Inc.
DS41399A-page 77
MCV18E
9.10.1
INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG of the OPTION register is
set, or falling if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF of the
INTCON register is set. This interrupt can be disabled
by clearing enable bit INTE of the INTCON register.
Flag bit INTF must be cleared in software in the Inter-
rupt Service Routine before re-enabling this interrupt.
The INT interrupt can wake-up the processor from
Sleep, if bit INTE was set prior to going into Sleep. The
status of Global Interrupt Enable (GIE) bit decides
whether or not the processor branches to the interrupt
vector following wake-up. See Section 9.13 “Power-
down Mode (Sleep)” for details on Sleep mode.
9.10.2
TMR0 INTERRUPT
An overflow (FFh
→ 00h) in the TMR0 register will set
flag bit T0IF of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing enable bit
T0IE of the INTCON register. (Section 4.0 “Timer0
9.10.3
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF of
the INTCON register. The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE of the
9.11
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt, (i.e., W register and
STATUS register). This will have to be implemented in
firmware.
Example 9-1 stores and restores the W, STATUS,
PCLATH and FSR registers. Context storage registers,
W_TEMP,
STATUS_TEMP,
PCLATH_TEMP
and
FSR_TEMP, must be defined in Common RAM which
are those addresses between 70h-7Fh in Bank 0 and
between F0h-FFh in Bank 1.
The example:
a)
Stores the W register.
b)
Stores the STATUS register in Bank 0.
c)
Stores the PCLATH register.
d)
Stores the FSR register.
e)
Executes the Interrupt Service Routine code
(User-generated).
f)
Restores all saved registers in reverse order
from which they were stored.
EXAMPLE 9-1:
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
W_TEMP
;Copy W to TEMP register, could be bank one or zero
SWAPF
STATUS,W
;Swap status to be saved into W
MOVWF
STATUS_TEMP
;Save status to bank zero STATUS_TEMP register
MOVF
PCLATH, W
;Only required if using pages 1, 2 and/or 3
MOVWF
PCLATH_TEMP
;Save PCLATH into W
CLRF
PCLATH
;Page zero, regardless of current page
BCF
STATUS, IRP
;Return to Bank 0
MOVF
FSR, W
;Copy FSR to W
MOVWF
FSR_TEMP
;Copy FSR from W to FSR_TEMP
:
:(ISR)
:
MOVF
FSR_TEMP,W
;Restore FSR
MOVWF
FSR
;Move W into FSR
MOVF
PCLATH_TEMP, W
;Restore PCLATH
MOVWF
PCLATH
;Move W into PCLATH
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
MOVWF
STATUS
;Move W into STATUS register
SWAPF
W_TEMP,F
;Swap W_TEMP
SWAPF
W_TEMP,W
;Swap W_TEMP into W
RETFIE
;Return from interrupt and enable GIE
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