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參數(shù)資料
| 型號： | MCV18ET-I/SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO18 |
| 封裝： | 7.50 MM, LEAD FREE, SOIC-18 |
| 文件頁數(shù)： | 83/108頁 |
| 文件大?。?/td> | 1509K |
| 代理商： | MCV18ET-I/SO |
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MCV18E
DS41399A-page 76
2009 Microchip Technology Inc.
9.10
Interrupts
The MCV18E devices have up to 7 sources of interrupt.
The Interrupt Control Register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE of the INTCON
register enables all unmasked interrupts when set, or
disables all interrupts when cleared. When bit GIE is
enabled, and an interrupt’s flag bit and mask bit are set,
the
interrupt
will
vector
immediately.
Individual
interrupts can be disabled through their corresponding
enable bits in various registers. Individual interrupt bits
are set, regardless of the status of the GIE bit. The GIE
bit is cleared on Reset and when an interrupt vector
occurs.
The “return-from-interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Registers, PIR1 and PIR2. The
corresponding interrupt enable bits are contained in
Special Function Registers, PIE1 and PIE2, and the
peripheral interrupt enable bit is contained in Special
Function Register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
FIGURE 9-13:
INTERRUPT LOGIC
Note:
Individual interrupt
flag bits
are
set
regardless
of
the
status
of
their
corresponding mask bit or the GIE bit.
ADIF
ADIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)
Interrupt to CPU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCV18E-I/P | 32-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDIP18 |
| MD8086-2/B | 16-BIT, 8 MHz, MICROPROCESSOR, CDIP40 |
| MD80C154-12/883D | 8-BIT, 12 MHz, MICROCONTROLLER, CDIP40 |
| MR83C154TXXX-20/883 | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154XXX-20/883D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC-V190H | 制造商:Panasonic Industrial Company 功能描述:FILTER KIT |
| M-CV193H | 制造商:Panasonic Industrial Company 功能描述:OD005 |
| MC-V193H | 制造商:Panasonic Industrial Company 功能描述:FILTER KIT |
| MCV19ES | 制造商:Mencom 功能描述: |
| MCV-19FP-FW | 制造商:Mencom 功能描述: |
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