參數(shù)資料
型號(hào)： MCV18ET-I/SO
元件分類(lèi)： 微控制器/微處理器
英文描述： FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO18
封裝： 7.50 MM, LEAD FREE, SOIC-18
文件頁(yè)數(shù)： 46/108頁(yè)
文件大?。?/td> 1509K
代理商： MCV18ET-I/SO
MCV18E
DS41399A-page 42
2009 Microchip Technology Inc.
7.1
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
7.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ADCON1 bits. See the corresponding Port
section for more information.
7.1.2
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 7.2
“ADC Operation” for more information.
7.1.3
ADC VOLTAGE REFERENCE
The PCFG bits of the ADCON1 register provide
independent control of the positive voltage reference.
The positive voltage reference can be either VDD or an
external voltage source.
7.1.4
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON0 register.
There are four possible clock options:
FOSC/2
FOSC/8
FOSC/32
FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 8-bit conversion requires 9.5 TAD periods.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
information. Table 7-1 gives examples of appropriate
ADC clock selections.
TABLE 7-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC
clock
frequency,
which
may
adversely affect the ADC result.
AD Clock Source (TAD)
Device Frequency
Operation
ADCS<1:0>
20 MHz
5 MHz
1.25 MHz
333.33 kHz
2TOSC
00
100 ns(2)
400 ns(2)
1.6
μs6 μs
8TOSC
01
400 ns(2)
1.6
μs6.4 μs
24
μs(3)
32 TOSC
10
1.6
μs6.4 μs
25.6
μs(3)
96
μs(3)
RC
11
2-6
μs(1), (4)
2-6
μs(1), (4)
2-6
μs(1), (4)
2-6
μs(1)
Legend: Shaded cells are outside of recommended range.
Note 1:
The RC source has a typical TAD time of 4
μs.
2:
These values violate the minimum required TAD time.
3:
For faster conversion times, the selection of another clock source is recommended.
4:
When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
Sleep operation only.
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