參數(shù)資料
型號: ML60852
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: USB Device Controller
中文描述: USB設(shè)備控制器
文件頁數(shù): 20/81頁
文件大小: 451K
代理商: ML60852
PEDL60852-01
1
Semiconductor
ML60852
20/81
(3) EP0 Transmit packet ready interrupt
This is used mainly during the transmission of a data packet in a control read transfer.
Operation
Source of operation
ML60852
Description (conditions, responses, etc.)
The EP0 transmit packet ready bit (D1 of EP0STAT) is de-
asserted during a control read transfer when the
processing has changed from the setup stage to the data
stage, and it is possible to write the transmit data to the
FIFO.
At this time, an interrupt is generated if the EP0 transmit
packet ready interrupt enable bit (bit D7 of INTENBL1) has
been asserted.
For the second and subsequent packets, in addition to this
condition, before the interrupt is generated, it is necessary
for an ACK response to come from the host for the packet
that has just been sent.
In the case of EP0 transmission, after the one packet of the
EP0 transmit data has been written in EP0TXFIFO, write a
“1” into the EP0 transmit packet ready bit (bit D1 of
EP0STAT). This puts the ML60852 in a state in which it
can transmit the data (that is, it can transmit the data packet
when an IN token arrives), and the
INTR
pin is de-asserted
at the same time.
Even when the number of bytes in the write data is less
than the maximum packet size, it is possible to transmit the
data by writing a “1” into the transmit packet ready status
bit. This makes it possible to transmit a short packet.
EP0 Transmit packet ready
interrupt generation
End of EP0 transmit
packet ready interrupt
Local MCU (firmware)
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