參數(shù)資料
型號(hào)： ML60852
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： USB Device Controller
中文描述： USB設(shè)備控制器
文件頁(yè)數(shù)： 26/81頁(yè)
文件大?。?/td> 451K
代理商： ML60852
PEDL60852-01
1
Semiconductor
ML60852
26/81
(11) Operation of 2-layer structure FIFO during bulk transfer
The FIFOs of EP1 and EP2 have a 64 bytes x 2-layer structure. Also, when EP4 is assigned for bulk transfer, its
FIFO also has a 64-bytes x 2-layer structure. As a consequence, these FIFOs can temporarily store a maximum of
128 bytes of bulk transfer data.
(1) 2-Layer reception operation (“O” indicates the assert condition and “x” indicates de-assert condition)
In the case of 1
→
2
→
3
→
4
→
5a
→
6
In the case of 1
→
2
→
3
→
4
→
5b
→
6
Layer A
64 bytes
Layer B
64 bytes
Layer A
PKT
RDY
Layer B
PKT
RDY
EPn
receive
PKT
RDY
x
INTR
1
2
Start storing data in layer A of reception
Data of one packet has been stored.
Start reception and storing of data in
layer B.
Local MCU starts reading layer A.
When the storing of packet in layer B is
completed following the completion of
reading layer A.
When the reading of packet in layer A is
completed following the completion of
storing data in layer B.
From 5a: Layer A has become empty.
From 5b: Layer B has become full.
Starting reading layer B also.
x
x
x
x
3
x
4
x
5a
5b
x
x
x
x
6
x
7
x
When one packet of receive data is stored in layer A of the FIFO and EOP is received, the ML60852 asserts the
packet ready bit of EPn and also asserts the
INTR
pin. This makes it possible for the local MCU to read the
receive data.
Subsequently, data can be received from the host, and the ML60852 switches the FIFO for storing to layer B.
When one packet of data described above has been read from layer A of the FIFO, make the local MCU reset the
receive packet ready status of EPn (by writing a “1” into bit D0 of EPnSTAT).
At the time the EPn receive packet ready status is reset, if the reception of layer B has not been completed, the
ML60852 resets the EPn receive packet ready status and de-asserts the
INTR
pin.
However, if the reception of layer B has been completed a the time the EPn receive packet ready status is reset,
the ML60852 rejects the request from the local MCU to reset the EPn receive packet ready status, and continues
to maintain the EPn receive packet ready status and the asserted condition of the
INTR
pin.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ML60852A 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller
ML60852ATBZ010 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ML60852ATBZ03A 制造商:ROHM Semiconductor 功能描述:
ML-60-V2/80721 制造商:Thomas & Betts 功能描述:
ML61 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Series Positive Voltage Detector
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