參數(shù)資料
型號(hào): ML60852
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: USB Device Controller
中文描述: USB設(shè)備控制器
文件頁數(shù): 64/81頁
文件大?。?/td> 451K
代理商: ML60852
PEDL60852-01
1
Semiconductor
ML60852
64/81
EP3 Status Register (EP3STAT)
Address
Type
Access type
0 x 63
Bit map
See below
D7
0
0
0
D6
0
0
0
D5
0
0
0
D4
0
0
0
D3
0
0
0
D2
0
0
0
D1
0
0
D0
0
0
After a hardware reset
After a bus reset
Definition
This register is valid only when EP3 has been set for bulk or interrupt transfer.
EP3 Receive packet ready bit (D0): This bit can be read by the local MCU. Also, this bit can be made “0” by
writing a “1” into bit D0. The asserting and de-asserting conditions of this bit
are as given below.
Bit name
Asserting condition
When an error-free packet is received. EP3 is locked.
Operation when asserted
EP3 Receive packet ready (D0)
Bit name
De-asserting condition
When the local MCU has reset (written
a “1” in) this bit.
Operation when de-asserted
Reception can be made by EP3.
EP3 Receive packet ready (D0)
EP3 Transmit packet ready bit (D1):This bit can be read by the local MCU. Also, this bit can be made “1” by
writing a“'1” into this bit. The asserting and de-asserting conditions of this bit
are as given below.
Bit name
Asserting condition
Operation when asserted
When an ACK message is received
from the host for the data transmission
from EP3.
EP1 Transmit packet ready (D1) When the local MCU has set this bit.
Bit name
De-asserting condition
Operation when de-asserted
Reception can be made by EP3.
EP1 Transmit packet ready (D1) Transmission can be made from EP3.
EP3 Receive packet
ready (Read/Reset)
EP3 Transmit packet ready
(Read/Set)
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