參數(shù)資料
型號(hào): ML60852
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: USB Device Controller
中文描述: USB設(shè)備控制器
文件頁(yè)數(shù): 60/81頁(yè)
文件大?。?/td> 451K
代理商: ML60852
PEDL60852-01
1
Semiconductor
ML60852
60/81
EP0 Status Register (EP0STAT)
Address
Type
Access type
0 x 60
Bit map
See below
D7
0
0
0
D6
0
0
0
D5
0
0
D4
0
0
D3
0
0
0
D2
0
0
D1
0
0
D0
0
0
After a hardware reset
After a bus reset
Definition
Setup ready:
This bit is set automatically when a setup packet normally arrives in the 8-byte setup register,
and the EP0 Receive FIFO is locked.
If INTENBL1(0) is asserted, the
INTR
pin is also asserted automatically when this bit is set.
The local MCU should write a “1” into this bit after reading out the 8-byte setup data.
When this is performed, the setup ready bit is reset and the
INTR
pin also is de-asserted.
During a control write transfer, the packet ready bit of EP0 is reset simultaneously and the
lock condition is released, and it becomes possible to receive packets by EP0 during the data
stage. The register will not change even if a “0” is written in this bit.
EP0 transmit packet
ready bit (D1):
The local MCU can read this bit. Writing when D1=1 sets this bit to “1”. The asserting and
de-asserting conditions are described below.
Bit name
Asserting condition
When the local MCU has reset this bit
Operation when asserted
Data can be transmitted from EP0.
EP0 transmit packet ready (D1)
Bit name
De-asserting condition
1. When an ACK is received from the
host for data transmission
2. When a setup packet is received
Operation when de-asserted
EP0 is locked. That is, an NAK is
automatically returned when an IN
token is sent from the host.
EP0 transmit packet ready (D1)
EP0 receive packet
ready (R/Reset)
EP0 stage (R)
00 = Default state
01 = Data stage
10 = Data stage completed state
EP0 transmit packet ready
(R/Set)
Setup ready
(R/Reset)
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