參數(shù)資料
型號: ML60852
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: USB Device Controller
中文描述: USB設(shè)備控制器
文件頁數(shù): 42/81頁
文件大?。?/td> 451K
代理商: ML60852
PEDL60852-01
1
Semiconductor
ML60852
42/81
DMA0,1 Control Registers (DMA0, 1CON)
Address
Type
Access type
0 x 10, 0 x 12
Bit map
Read/Write
D7
0
D6
0
D5
0
The previous value is retained
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
Note 1:During the 16-bit mode, the higher order byte of the leading word will be 00h.
Note 2:The higher order byte and the lower order byte are allocated in the little-endian sequence. That is,
the LSB corresponds to AD0 to AD7 and the MSB corresponds to D8 to D15.
During the 16-bit mode and when the packet size is an odd number of bytes, the higher order byte
of the last word will be 00h.
Note 3:When the EP specifications for the DMA channels 0 and 1 both have the same values, DREQ0,
DREQ 1 and DACK0, DACK 1 will respectively be equivalent.
Note 4:The settings of all bits other than bit D7, that is, of bits D0 to D6 should be completed at the time
of initialization (at the latest, before a token packet for EP1 to Ep5 arrives), and should not be
altered thereafter. Write a “1” to D7 in order to temporarily stop DMA transfer in the middle.
When the transfer is restarted by writing a “0” to D7, it is possible to restart the transfer from the
byte (or word) next to the one at which the transfer was interrupted.
DMA Enable
0 = DMA Disabled
1=DMA Enabled
DMA Transfer data width
0 = Byte width (8 bits)
1 = Word width (16 bits) (Note 2)
DMA Transfer mode
0=Single transfer mode
1=Demand transfer mode
DMA Address mode
0 = Single address mode
1 = Dual address mode
DMA Byte count
0 = The number of bytes is not
inserted
1 = The data of the number of
bytes is inserted in the
leading byte or leading word
of the transfer data. (Note 1)
EP Specification
Specifies the target EP for the DMA transfer
0=EP1, 1=Ep2, 2=EP4, 3=EP5 (Note 3)
DMA Interrupting (Note 4)
0=Normal operation
1=The
DREQ
pin is de-asserted
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