參數(shù)資料
型號(hào): ML60852
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: USB Device Controller
中文描述: USB設(shè)備控制器
文件頁(yè)數(shù): 59/81頁(yè)
文件大?。?/td> 451K
代理商: ML60852
PEDL60852-01
1
Semiconductor
ML60852
59/81
EP3 Receive Byte Counter Register (EP3RXCNT)
Address
Type
Access type
0 x 5B
6-Bit data
Read only
D7
0
0
0
D6
0
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
After a hardware reset
After a bus reset
Definition
Receive byte count (R)
The ML60852 automatically counts the number of bytes in the packet being received. Although the counting is
done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case
of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value
and reads out the data of one packet from the EP3 Receive FIFO.
This register will be invalid when the transfer direction of the EP is set for transmission.
The EP3RXCNT register is cleared under the following conditions.
1. When an OUT token is received for EP3.
2. When the local MCU resets the EP receive packet ready bit.
3. When the local MCU writes a “0” into the stall bit.
EP4, 5 Receive Byte LSB Counter Registers (EP4, 5RXCNTLSB)
Address
Type
Access type
0 x 5C, 5D
10-Bit or 9-bit data
Read only
D7
0
0
D6
0
0
D5
0
0
Receive byte count LSB (R)
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
After a hardware reset
After a bus reset
Definition
The ML60852 automatically counts the number of bytes in the packet being received. Although the counting is
done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case
of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value
and reads out the data of one packet from the EP4/5 Receive FIFO. The lower 8 bits of the receive byte count are
stored in this register and the higher order bits are stored in the EP receive byte counter MSB.
This register will be invalid when the transfer direction of the EP is set for transmission.
The EP4,5RXCNT register is cleared under the following conditions.
1. When an OUT token is received for the EP.
2. When the local MCU resets the EP receive packet ready bit.
3. When the local MCU writes a “0” into the stall bit.
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參數(shù)描述
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