參數(shù)資料
型號： MNSC140CORE
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號處理器
文件頁數(shù)： 15/88頁
文件大?。?/td> 983K
代理商： MNSC140CORE
Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
1-5
HD[32–39
]
D[32–39]
Reserved
Input/ Output
Input/ Output
Input
Host Data Bus 32–39
Bits 32–39 of the DSI data bus.
System Bus Data 32–39
For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives
valid data on this bus.
If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can
be left unconnected.
HD40
D40
ETHRXD0
Input/ Output
Input/ Output
Input
Host Data Bus 40
Bit 40 of the DSI data bus.
System Bus Data 40
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
Ethernet Receive Data 0
In MII and RMII modes, bit 0 of the Ethernet receive data.
HD41
D41
ETHRXD1
Input/ Output
Input/ Output
Input
Host Data Bus 41
Bit 41 of the DSI data bus.
System Bus Data 41
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
Ethernet Receive Data 1
In MII and RMII modes, bit 1 of the Ethernet receive data.
HD42
D42
ETHRXD2
Reserved
Input/ Output
Input/ Output
Input
Input
Host Data Bus 42
Bit 42 of the DSI data bus.
System Bus Data 42
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
Ethernet Receive Data 2
In MII mode only, bit 2 of the Ethernet receive data.
In RMII mode, this pin is reserved and can be left unconnected.
HD43
D43
ETHRXD3
Reserved
Input/ Output
Input/ Output
Input
Input
Host Data Bus 43
Bit 43 of the DSI data bus.
System Bus Data 43
For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives
valid data on this bus.
Ethernet Receive Data 3
In MII mode only, bit 3 of the Ethernet receive data.
In RMII mode, this pin is reserved and can be left unconnected.
HD[44–45
]
D[44–56]
Reserved
Input/ Output
Input/ Output
Input
Host Data Bus 44–45
Bits 44–45 of the DSI data bus.
System Bus Data 44–45
For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives
valid data on this bus.
If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can
be left unconnected.
Table 1-5.
DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
Type
Description
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