參數(shù)資料
型號: MNSC140CORE
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: Quad Core 16-Bit Digital Signal Processor
中文描述: 四核16位數(shù)字信號處理器
文件頁數(shù): 30/88頁
文件大小: 983K
代理商: MNSC140CORE
MSC8122 Technical Data, Rev. 13
1-20
Freescale Semiconductor
Signals/Connections
GPIO14
TDM2RDAT
IRQ12
ETHRXD0
NC
Input/ Output
Input/ Output
Input
Input
Input
Input
General-Purpose Input Output 14
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122
Reference Manual
GPIO programming model.
TDM2 Serial Receiver Data
The receive data signal for TDM 2. As an input, this can be the DATA_A data signal for TDM 2. For
configuration details, refer to the
MSC8122
Reference Manual
chapter describing TDM operation.
Interrupt Request 12
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
Ethernet Receive Data 0
Bit 0 of the Ethernet receive data (MII and RMII).
Not Connected
For SMII mode, this signal must be left unconnected.
GPIO15
TDM1TSYN
DREQ1
Input/ Output
Input/ Output
Input
General-Purpose Input Output 15
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122 Reference Manual
GPIO programming model.
TDM1 Transmit frame Sync
Transmit Frame Sync for TDM 1.
DMA Request 1
Used by an external peripheral to request DMA service.
GPIO16
TDM1TCLK
DONE1
DRACK1
Input/ Output
Input
Input/ Output
Output
General-Purpose Input Output 16
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122 Reference Manual
GPIO programming model.
TDM1 Transmit Clock
Transmit Clock for TDM 1.
DMA Done 1
Signifies that the channel must be terminated. If the DMA controller generates DONE, the channel
handling this peripheral is inactive. As an input to the DMA controller, DONE closes the channel much like
a normal channel closing.
See the
MSC8122 Reference Manual
chapters on DMA controller and GPIO for information on
configuring the DRACK or DONE mode and pin direction.
DMA Data Request Acknowledge 1
Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request.
GPIO17
TDM1TDAT
DACK1
Input/ Output
Input/ Output
Output
General-Purpose Input Output 17
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122
Reference Manual
GPIO programming model.
TDM1 Serial Transmitter Data
The transmit data signal for TDM 1. As an output, this can be the DATA_D data signal for TDM 1.For
configuration details, refer to the
MSC8122
Reference Manual
chapter describing TDM operation.
DMA Acknowledge 1
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
Table 1-7.
GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Signal Name
Type
Description
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