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參數(shù)資料
| 型號(hào)： | MNSC140CORE |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Quad Core 16-Bit Digital Signal Processor |
| 中文描述： | 四核16位數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 43/88頁 |
| 文件大?。?/td> | 983K |
| 代理商： | MNSC140CORE |
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AC Timings
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
2-9
2.5.4.3 Reset Timing Tables
Table 2-11
and
Figure 2-4
describe the reset timing for a reset configuration write through the direct slave
interface (DSI) or through the system bus.
Table 2-11.
Timing for a Reset Configuration Write through the DSI or System Bus
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
CLKIN = 20 MHz
CLKIN = 100 MHz (300 MHz core)
CLKIN = 133 MHz (400 MHz core)
CLKIN = 166 MHz (500 MHz core)
16/CLKIN
800
160
120
96
—
—
—
—
ns
ns
ns
ns
2
Delay from deassertion of external PORESET to deassertion of internal
PORESET
CLKIN = 20 MHz to 166 MHz
1024/CLKIN
6.17
51.2
μs
3
Delay from de-assertion of internal PORESET to SPLL lock
CLKIN = 20 MHz (RDF = 1)
CLKIN = 100 MHz (RDF = 1) (300 MHz core)
CLKIN = 133 MHz (RDF = 2) (400 MHz core)
CLKIN = 166 MHz (RDF = 2) (500 MHz core)
6400/(CLKIN/RDF)
(PLL reference clock-
division factor)
320
64
96
77
320
64
96
77
μs
μs
μs
μs
5
Delay from SPLL to HRESET deassertion
REFCLK = 40 MHz to 166 MHz
512/REFCLK
3.08
12.8
μs
6
Delay from SPLL lock to SRESET deassertion
REFCLK = 40 MHz to 166 MHz
Setup time from assertion of
RSTCONF
, CNFGS, DSISYNC, DSI64,
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
Hold time from deassertion of PORESET to deassertion of
RSTCONF
,
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
515/REFCLK
3.10
12.88
μs
7
3
—
ns
8
5
—
ns
Note:
Timings are not tested, but are guaranteed by design.
Figure 2-4.
Timing Diagram for a Reset Configuration Write
PORESET
Input
Internal
HRESET
Output (I/O)
SRESET
Output (I/O)
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]
pins are sampled
Host programs
Reset Configuration
Word
SPLL is locked
(no external indication)
PORESET
1
2
MODCK[3–5]
1 + 2
3
5
6
SPLL
locking period
Reset configuration write
sequence during this
period.
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