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參數資料
| 型號： | MSM7630 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Universal Speech Processor(通用語音處理器) |
| 中文描述： | 通用語音處理器（通用語音處理器） |
| 文件頁數： | 26/89頁 |
| 文件大?。?/td> | 430K |
| 代理商： | MSM7630 |
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MSM7630
Semiconductor
26/89
bit[12] Z: Zero (read-only)
Indicates that execution of an addition or subtraction instruction resulted in a zero value (bit[31:0]
are all "0").
bit[10] ICP: Instruction Cache Purge (read/write)
Invalidates all instruction cache entries. Writing "1" to this bit purges the contents of the instruction
cache. After this process (after one cycle) this bit is automatically cleared to "0" by hardware. The
instruction cache is purged during reset.
bit[9] ICL: Instruction Cache Lock (read/write)
Freezes all instruction cache entries. After "1" is written to this bit, instruction cache contents are
frozen and then instruction execution continues. This bit will be "1" after reset.
bit[8] NOP: Non-Operation (read-only)
When set to "1", forces the next instruction to a NOP regardless of the instruction. There is no way
to directly set this bit to "1". This bit will be "0" after reset.
bit [5] EBP: Breakpoint Trap Enable (read/write)
Enables breaks. If this bit is set to "1", then a trap will occur when the value of the instruction
execution address (%PC) equals the value of the breakpoint address (%BPA). The instruction that
generated the break will not be executed. This bit will be "0" after reset.
bit[4] EM: Master Enable (read/write)
Disables all exceptions, interrupts, and traps. This bit automatically becomes "0" at the point when
the processor accepts an exception, interrupt, or trap. While this bit is "0", further exceptions,
interrupts or traps will not be accepted, with instruction execution continuing in the normal
instruction sequence. An instruction must be used to return this bit to "1". It will be "0" after reset.
bit[3:0] PL: Processor Level (read/write)
Sets and provides the processor’s instruction execution level. Processor levels are 0-15. An external
interrupt will be accepted if its level has a higher priority than the processor level at that time.
External interrupt levels are 1-16, so when PL is 0 all external interrupts will be accepted, and when
PL is 1 external interrupts of level 2 and above will be accepted. When an external interrupt is
accepted, the processor level will become the same as the external interrupt level. For example, if
PL is 5 and a level 7 external interrupt is accepted, then PL will transition to 7 at that point. When
PL is restored to its previous state, its saved value in %prPSR will be restored to %PSR.
Alternatively PL can be set to its previous value explicitly by an instruction in the interrupt process
routine. However, %PSR is a privileged register, so writes are only permitted in supervisor mode.
PL will be set to 15 after reset.
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相關代理商/技術參數 |
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| MSM7653 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:NTSC/PAL Digital Video Encoder |
| MSM7653GS-2K | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:NTSC/PAL Digital Video Encoder |
| MSM7654 | 制造商:ROHM Semiconductor 功能描述: |
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