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參數(shù)資料
| 型號： | MSM7630 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Universal Speech Processor(通用語音處理器) |
| 中文描述： | 通用語音處理器（通用語音處理器） |
| 文件頁數(shù)： | 45/89頁 |
| 文件大?。?/td> | 430K |
| 代理商： | MSM7630 |
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MSM7630
Semiconductor
45/89
bit[20:18] AWW: SRAM Write Wait (read/write)
These bits set the wait count when SRAM space is accessed by a write.
AWW = 000
AWW = 001
AWW = 010
AWW = 011
AWW = 100
AWW = 101
AWW = 110
AWW = 111
2
t
access (1 wait)
3
t
access (2 waits)
4
t
access (3 waits)
5
t
access (4 waits)
6
t
access (5 waits)
8
t
access (7 waits)
10
t
access (9 waits)
12
t
access (11 waits)
These bits will be "111" after reset.
bit[17:16] AS: SRAM Device Size (read/write)
These bits set the device size of SRAM space.
AS = 00
AS = 01
AS = 10
AS = 11
No SRAM (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
These bits will be "00" after reset. When this field is "00", attempting to access SRAM space will
cause an instruction access exception or data access exception.
bit[14] OC: ROM Parity Check (read/write)
This bit sets parity checking for ROM space. It will be "0" after reset.
OC = 0
OC = 1
Ignore parity errors.
Generate a bus error if a parity error is detected.
This bit will be "0" for the MSM7630.
bit[13] OD: ROM Dummy Cycle (read/write)
This bit sets whether or not a ROM space access will immediately follow an SRAM space or DRAM
space read.
OD = 0
OD = 1
Consecutive access enabled.
Force an interval of at least one clock.
This bit will be "1" after reset.
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