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參數(shù)資料
| 型號： | MSM7630 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Universal Speech Processor(通用語音處理器) |
| 中文描述： | 通用語音處理器（通用語音處理器） |
| 文件頁數(shù)： | 66/89頁 |
| 文件大?。?/td> | 430K |
| 代理商： | MSM7630 |
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MSM7630
Semiconductor
66/89
5.1.2 Clock Synchronized Transmit Operation
1) Verify that the SSTS (Status Register) SOST bit is "1", and then write the data to be transferred to
the transmit buffer SOB.
2) Write "0" to SOST to indicate that SOB has valid data.
3) If using SIO interrupts, set the SCMD (Command Register) SIEN bit to "1". If using the transmit
buffer empty interrupt, write "1" to the SCMD STXIE bit. If using the transmit end interrupt, write
"1" to the SCMD STEIE bit.
4) If the MCMD (Modem Command Register) SAEN bit is "0", then setting the SCMD (Command
Register) STEN bit to "1" will start the transfer. If the MCMD SAEN bit is "1", then the transfer will
start when the SCMD STEN bit is "1" and the CTS input is "1".
5) SOB (Transmit Buffer) data will be transferred LSB first from the TXD output. Also, a synchronous
clock will be transmitted from the SCLK pin. Data on the TXD output will change synchronous
to the falling edge of SCLK. The receiving device should sample TXD data on the rising edge of
SCLK.
6) When the next data can be written to the transmit buffer, the SSTS (Status Register) SOST bit will
change from "0" to "1". If the SCMD (Command Register) STXIE and SIEN bits are "1" at this time,
then the SSTS STXI bit will become "1" and an interrupt request to the CPU will be generated.
7) For continuous transfers, after the SSTS (Status Register) SOST bit becomes "1" write new data to
SOB (Transmit Buffer) and write "0" to the SOST bit.
8) If there is no more data to be transmitted, then write "0" to the SCMD (Command Register) STXIE
bit. This will disable interrupt requests from SIO.
9) When transfer of the eighth bit of data ends, the SSTS (Status Register) SOST bit will become "1"
(transmit buffer SOB is empty), SCLK will stop, and the transmit operation will end. If the
SCMD’s STEIE and SIEN bits are "1" at this time, then the SSTS’s STEI bit will become "1" and an
interrupt request to the CPU will be generated. This interrupt can be released by writing "0" to the
SSTS’s STEI bit or the SCMD’s STEIE bit.
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