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參數(shù)資料
| 型號(hào)： | MSM7630 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Universal Speech Processor(通用語音處理器) |
| 中文描述： | 通用語音處理器（通用語音處理器） |
| 文件頁數(shù)： | 48/89頁 |
| 文件大?。?/td> | 430K |
| 代理商： | MSM7630 |
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MSM7630
Semiconductor
48/89
3.5 DRAM: DRAM Configuration Register
This register sets DRAM space.
31
28 27 26 25 24
TP
23 22 21 20
18 17 16
RA
CS
15
13 12 11 10 9
SZ
R
F
M
E
M
0
RFC
bit
0
29
0
0
DT
D
P
MD
CA
After this register has been written, DRAM must not be accessed until the DRAM is operating
properly. Refer to the data sheet of the DRAM used to obtain the required conditions for proper
DRAM operation.
bit[28:27] DT: Device Type (read/write)
These bits set the DRAM device type.
DT = 00
DT = 01
High-speed page mode
Hyper-page mode (EDO DRAM)
These bits will be "00" after reset.
bit[26] PR: Parity Check (read/write)
This bit sets parity checking for DRAM space. It will be "0" after reset.
PR = 0
PR = 1
Ignore parity errors.
Generate a bus error if a parity error is detected.
This bit will be "0" for the MSM7630.
bit[25:24] TP: Type (read/write)
This bit sets the DRAM’s RAS signal and byte position control signal.
TP = 00
TP = 01
TP = 10
TP = 11
1 RAS mode, byte position CAS control
2 RAS mode, byte position CAS control
1 RAS mode, byte position WE control
2 RAS mode, byte position WE control
These bits will be "00" after reset.
bit[23] DP: Data Priority (read/write)
This bit sets the priority of processing when data access is requested by a load/store instruction
during a one-line instruction cache read from DRAM due to an instruction cache miss.
DP = 0
DP = 1
Give priority to the instruction cache read from DRAM.
Give priority to the data access.
This bit will be "0" after reset.
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