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MT90500
102
Table 51 - Local Bus Type Register
Address: 6020 (Hex)
Label: LBTYP
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
LBUSFS
1:0
R/W
Local Bus Fsync type.
“00” = negative polarity for half-cycle of LOCx1, straddling the frame boundary (SCSA/
MVIP/H-MVIP/ST-BUS);
“01” = Reserved;
“10” = Reserved;
“11” = positive polarity for full-cycle of LOCx1, preceding the frame boundary (IDL).
LBUSSMPL
3:2
R/W
Local Bus Sampling.
“00” = 4/4;
“01” = 3/4;
“10” = 2/4;
“11” = Reserved.
Reserved
5:4
R/W
Reserved. Should be written as “00”.
LCLKDIV
7:6
R/W
Local Bus Clock Division factor. Amount that TDM backplane clock must be divided to
generate 2.048 Mbps local bus.
“00” = Direct;
“01” = Divided by 2;
“10” = Divided by 4;
“11” = Reserved.
STi2LOCSTo
11:8
R/W
Indicates which input TDM stream will be routed to LOCSTo.
LOCSTi2STo
15:12
R/W
Indicates on which output TDM stream LOCSTi will be routed.
Table 52 - TDM Bus to Local Bus Transfer Register
Address: 6022 (Hex)
Label: TDMLOC
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
TDM2LOCTS
6:0
R/W
LOCSTo TDM Time Slot. Input TDM time slot which will be transmitted out on LOCSTo
time slot 0.
Reserved
7
R/W
Reserved. Should be written as ‘0’.
LOCSToNUM
14:8
R/W
LOCSTo Number of Time Slots. Number of time slots that are passed from the TDM bus to
the local bus.
“0000000” = 1 channel;
“0011111” = 32 channels.
TENA
15
R/W
Transfer Enable. When ‘0’, the transfer process from the TDM bus to the local bus is
disabled. When ‘1’, the transfer is enabled.
Whenever the transfer of data from the TDM bus to the local bus is disabled (either
because this bit is ‘0’ or because the specified number of time slots has been transferred),
LOCSTi and LOCSTo are internally connected and operate in loopback mode.
Note:
the TIENE bit at register 6000h must be set to ‘1’ (TDM to/from Internal Memory
transfer enabled) for the Local Bus to/from TDM Bus transfer to operate.