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參數(shù)資料
| 型號(hào)： | MT90500 |
| 廠(chǎng)商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 11/159頁(yè) |
| 文件大小： | 514K |
| 代理商： | MT90500 |
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MT90500
11
1.
Introduction
1.1
Functional Overview
The Mitel MT90500 Multi-Channel AAL1 SAR bridges a standard isochronous TDM (Time Division Multiplexed)
backplane to a standard ATM (Asynchronous Transfer Mode) bus. On the TDM bus side, the MT90500 can
interface to 16 bidirectional TDM bus links operating at 2.048, 4.096 or 8.192 Mbps (compatible with MVIP / H-
MVIP, SCSA and Mitel ST-BUS). On the ATM interface side, the MT90500 provides the UTOPIA bus
standardized by the ATM Forum. The device provides the AAL1 Structured Data Transfer (referred to as SDT
from now on in this document) and pointerless Structured Data Transfer mappings defined by ANSI T1.630-
1993 and ITU-T I.363. In addition, the MT90500 provides CBR (Constant Bit Rate) mapping of TDM to AAL0,
and to AAL5 (CBR-AAL5). In all data transfer formats, the user simply ports the T1/E1, T3/E3, etc. traffic onto
the TDM backplane before applying it to the MT90500. As well, the device also supports TDM clock recovery
using adaptive, SRTS, or external clock recovery.
In the receive direction, ATM cells with VCs destined for the MT90500 are extracted from the UTOPIA bus and
sent toward the TDM interface. In the transmit direction, the MT90500 provides multiplexing capabilities at the
UTOPIA interface to allow the use of an external AAL5 SAR device, or multiple MT90500 devices. This is useful
when CBR data and VBR/ABR/UBR data traffic must be transmitted from the local node on the same physical
link. As well, the ability to multiplex internal AAL1 cells with external AAL5 cells can be used to interleave
associated signalling cells and control messages with the AAL1 CBR traffic.
The MT90500 also offers some internal support for non-CBR data traffic. If the application's signalling (non-
CBR) data throughput is not high, the MT90500 can transmit and receive AAL5 (or other non-CBR data) to /
from a pair of FIFOs. This requires the microprocessor to perform SAR functions via software, but may remove
the requirement for an external data SAR. Alternatively, if standard AAL5 signalling is not required by the
system, the user can use some TDM channels for HDLC or proprietary signalling.
Segmentation and reassembly of TDM data to / from ATM cells is highly flexible. The MT90500 allows the user
to select one or more TDM channels to be carried on an ATM logical connection with associated VPI/VCI. The
number of TDM channels (1 to 122), the VPI/VCI, the data transfer method (SDT or pointerless Structured Data
Transfer), cell partial-fill level, and the AAL (AAL1, CBR-AAL5, or CBR-AAL0) are all programmable. The time
slot assignment circuit has 64 kbps granularity and allows a group of TDM channels to be carried on a single
ATM logical channel (channel grooming). There is no limitation for distributing n x 64 channels on the TDM bus
(i.e. TDM channels on a given VC can be concatenated or dispersed anywhere on the 16 serial data streams).
Up to 1024 bidirectional virtual circuits (VCs) can be handled simultaneously by the internal AAL1 processors.
At the maximum TDM rate of 8.192 Mbps, up to 2048 input/output 64 kbps channels are available (1024
bidirectional TDM channels). If the ATM VCs are carrying multiple TDM channels (n x 64), less VCs will be
created. The user is given the ability to flexibly define which 64 kbps channels will be converted into ATM VCs.
It should be noted that since the MT90500’s serial TDM port is fully bidirectional, the ATM logical connections
can be defined as full duplex channels (e.g. voice conversation) or one-way connections (e.g. video playback).
Using the full duplex capabilities, up to 1024 simultaneous phone calls could be handled by the MT90500.
The MT90500 allows the user to scale the size of the external synchronous memory to suit the application. The
external memory’s size is influenced by the number of virtual circuits required, the number of TDM channels
being handled, and the amount of cell delay variation (CDV) tolerance required for the receive VCs. User-
defined lookup tables, data cell FIFOs, and multiple event schedulers also influence the amount of external
memory required.
The MT90500 supports two clocking schemes on the TDM bus: clock master and clock slave. In clock master,
the MT90500 drives the clocks onto the TDM backplane (the TDM clock is recovered from an incoming ATM
VC, or from an external source). In clock slave mode, the MT90500 receives its 8 kHz framing and clocks
(4.096, 8.192 or 16.384 MHz) from the TDM backplane, and times its internal functions from that.
Figure 1 on page 12 shows the MT90500 block diagram. The Applications section of this document illustrates
several connectivity options with external PHY and SAR devices.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線(xiàn)的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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